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LFEC10 Datasheet(PDF) 24 Page - Lattice Semiconductor |
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LFEC10 Datasheet(HTML) 24 Page - Lattice Semiconductor |
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24 / 163 page ![]() 2-21 Architecture Lattice Semiconductor LatticeECP/EC Family Data Sheet For further information about the sysDSP block, please see the list of technical information at the end of this data sheet. Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O buffer, and receives input from the buffer. Figure 2-24. PIC Diagram Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25. The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16 PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight bits of data. PIO B PADA "T" PADB "C" OPOS0 ONEG0 OPOS1 ONEG1 TD INCK INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN PIO A sysIO Buffer DQS DDRCLKPOL IOLD0 IOLT0 D0 DDRCLK DI IPOS1 IPOS0 INCK INDD INFF D0 D1 TD D1 Output Register Block (2 Flip Flops) Tristate Register Block (2 Flip Flops) DDRCLK Input Register Block (5 Flip Flops) CLKO CLKI CEO CEI Control Muxes LSR GSR |
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