| Electronic Components Datasheet Search |
|
6V7 Datasheet(PDF) 104 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
6V7 Datasheet(HTML) 104 Page - Renesas Technology Corp |
|
104 / 298 page ![]() Rev.1.00 May 18, 2004 page 104 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP Figure 2.11.4 UARTi transmit buffer register (i = 0 and 2) b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmit data (Note) Nothing is assigned. In an attempt to write to these bits, write “0.” The value, if read, turns out to be indeterminate. Symbol Address When reset U0TB 03A316, 03A216 Indeterminate U2TB 037B16, 037A16 Indeterminate W R Figure 2.11.5 UARTi receive buffer register (i = 0 and 2) Symbol Address When reset U0RB 03A716, 03A616 Indeterminate U2RB 037F16, 037E16 Indeterminate b7 b0 (b15) (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit name Bit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note 1) Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. In an attempt to write to these bits, write “0.” The value, if read, turns out to be “0.” Receive data W R Receive data Reserved bit Must always be set to “0” Must always be set to “0” Notes 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0.”) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16 and 037E16) is read out. 2: The Receive Buffer Register (received data and error flag) must be read in one operation by accessing it wordwise. 0 Figure 2.11.6 UARTi bit rate generator (i = 0 and 2) UARTi bit rate generator b7 b0 Symbol Address When reset U0BRG 03A116 Indeterminate U2BRG 037916 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R *1 Before writing any value, make sure no transmit or receive operation is forbiddew. *2 Use the MOV instruction to write to this register. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |