6V7 datasheet(105/298 Pages) RENESAS

105 / 298 page

Rev.1.00

May 18, 2004

page 105 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

UART2 transmit/receive mode register

Symbol

Address

When reset

U2MR

037816

0016

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock

1 : External clock

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity

reverse bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 : No reverse

1 : Reverse

Usually set to “0”

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

0 : Internal clock

1 : External clock

Invalid

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Invalid

0 : No reverse

1 : Reverse

Usually set to “0”

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

UART0 transmit/receive mode register

Symbol

Address

When reset

U0MR

03A016

0016

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock

1 : External clock

Stop bit length select bit

Odd/even parity select bit

Reserved bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

Must always be set to “0”

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

b2 b1 b0

0 : Internal clock

1 : External clock

Invalid

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Invalid

Must always be set to “0”

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Figure 2.11.7 UART0 transmit/receive mode register

Figure 2.11.8 UART2 transmit/receive mode register

6V7 Datasheet(PDF) 105 Page - Renesas Technology Corp

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