6V7 datasheet(119/298 Pages) RENESAS

119 / 298 page

Rev.1.00

May 18, 2004

page 119 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Figure 2.11.20 UART0 transmit/receive mode register in UART mode

Symbol

Address

When reset

U0MR

03A016

0016

CKDIR

UART0 transmit/receive mode register

Internal / external clock

select bit

STPS

PRY

PRYE

IOPOL

0 : Internal clock

1 : External clock

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

Must always be set to “0”

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Stop bit length select bit

Odd / even parity

select bit

Parity enable bit

Reserved bit

Figure 2.11.21 UART2 transmit/receive mode register in UART mode

Symbol

Address

When reset

U2MR

037816

0016

CKDIR

UART2 transmit/receive mode register

Internal / external clock

select bit

STPS

PRY

PRYE

IOPOL

0 : Internal clock

1 : External clock

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 : No reverse

1 : Reverse

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

Stop bit length select bit

Odd / even parity

select bit

Parity enable bit

TxD, RxD I/O polarity

reverse bit (Note)

Note: Usually set to “0”.

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