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6V7 Datasheet(PDF) 123 Page - Renesas Technology Corp |
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6V7 Datasheet(HTML) 123 Page - Renesas Technology Corp |
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123 / 298 page  Rev.1.00 May 18, 2004 page 123 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP (1) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 2.11.24 shows the ex- ample of timing for switching serial data logic. Figure 2.11.24 Timing for switching serial data logic ST : Start bit P : Even parity SP : Stop bit D0 D1 D2 D3 D4 D5 D6 D7 P SP ST SP ST D3 D4 D5 D6 D7 P D0 D1 D2 Transfer clock TxD2 (no reverse) TxD2 (reverse) “H” “L” “H” “L” “H” “L” • When LSB first, parity enabled, one stop bit (2) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. |
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