6V7 datasheet(129/298 Pages) RENESAS

129 / 298 page

Rev.1.00

May 18, 2004

page 129 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Fig. 2.11.30 I2Ci port selection register (i = 0, 1)

(1) I2Ci port selection register (i = 0, 1)

The I2Ci port selection register consists of bit to validate the multi-master I2C-BUS interface i function.

s Bit 0: TXD2, RXD2 port select bit

Note: I2C0 Port Selection Register only

When using UART2, setting bit to “0” causes P70 and P71 to function respectively as TXD2 and RXD2,

and setting bit to “1” causes P93 and P94 to function respectively as TXD2 and RXD2.

Note that the multimaster I2C-BUS interface enable bit (FIICON) described later has priority over this

bit.

s Bit 2: Multi-master I2C-BUS interface valid bit (FIICON)

When this bit is “0”, the multi-master I2C-BUS interface i is nonactive; when “1”, it is active. When

selecting active, multi-master I2C-BUS interface 0 is connected with the ports selected by bits 0 and 1

of the peripheral mode register (address 027D16) and multi-master I2C-BUS interface 1 is connected

with the ports P93 and P94.

Note: It needs 20-BCLK cycles from setting this bit to “1” to being active of multi-master I2C-BUS

interface i. Accordingly, do not access multi-master I2C-BUS interface i-related registers in this

period.

I2C0 port selection register

b3 b2 b1 b0

Symbol

Address

When reset

IIC0S2D

02E516

00?000002

TXD2 and RXD2

port select bit

PSEL0

Bit Symbol

Bit name

Function

FIICON

Multi-master I

2C-BUS

interface valid bit

0 : Nonactive

1 : Active

0 : P70 and P71

1 : P93 and P94

Must always be set to “0”

Reserved bits

Must always be set to “0”

Reserved bits

I2C1 port selection register

b3 b2 b1 b0

Symbol

Address

When reset

IIC1S2D

02ED16

00?000002

FIICON

Multi-master I

2C-BUS

interface valid bit

0 : Nonactive

1 : Active

Must always be set to “0”

Reserved bits

Must always be set to “0”

Reserved bits

Bit Symbol

Bit name

Function

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