6V7 datasheet(140/298 Pages) RENESAS

140 / 298 page

Rev.1.00

May 18, 2004

page 140 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Item

Standard Clock Mode

High-speed Clock Mode

Setup time (Min.)

5.6

µs

2.1

µs

Hold time (Min.)

4.8

µs

2.3

µs

Set/reset time for BB flag

3.5

µs

0.75

µs

(7) START condition generation method

When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register

to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit

counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and

BB bit set timing are different in the standard clock mode and the high-speed clock mode. Refer to

Figure 2.11.38 for the START condition generation timing diagram, and Table 2.11.9 for the START

condition/STOP condition generation timing table.

(8) STOP condition generation method

When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register

for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be

generated. The STOP condition generation timing and the BB flag reset timing are different in the

standard clock mode and the high-speed clock mode. Refer to Figure 2.11.39 for the STOP condition

generation timing diagram, and Table 2.11.9 for the START condition/STOP condition generation

timing table.

Fig. 2.11.38 START condition generation timing diagram

Fig. 2.11.39 STOP condition generation timing diagram

Table 2.11.9 START condition/STOP condition generation timing table

I2Ci status register write signal

Set time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

I2Ci status register write signal

Reset time

for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

6V7 Datasheet(PDF) 140 Page - Renesas Technology Corp

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