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6V7 Datasheet(PDF) 141 Page - Renesas Technology Corp |
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6V7 Datasheet(HTML) 141 Page - Renesas Technology Corp |
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141 / 298 page  Rev.1.00 May 18, 2004 page 141 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP Standard Clock Mode High-speed Clock Mode 6.5 µs < SCL release time 1.0 µs < SCL release time 3.25 µs < Setup time 0.5 µs < Setup time 3.25 µs < Hold time 0.5 µs < Hold time (9) START/STOP condition detect conditions The START/STOP condition detect conditions are shown in Figure 2.11.40 and Table 2.11.10. Only when the 3 conditions of Table 2.11.10 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal <IICIRQ> is generated to the CPU. Fig. 2.11.40 START condition/STOP condition detect timing diagram Table 2.11.10 START condition/STOP condition detect conditions Hold time Setup time SCL SDA (START condition) SDA (STOP condition) SCL release time Hold time Setup time |
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