SH7136 datasheet(107/1160 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 Sep. 10, 2008 Page 81 of 1130

REJ09B0402-0200

5.3

Address Errors

5.3.1

Address Error Sources

Address errors occur when instructions are fetched or data is read from or written to, as shown in

table 5.6.

Table 5.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus Master

Bus Cycle Description

Address Errors

CPU

Instruction fetched from even address

None (normal)

Instruction

fetch

Instruction fetched from odd address

Address error occurs

Instruction fetched from a space other than

on-chip peripheral module space

None (normal)

Instruction fetched from on-chip peripheral

module space

Address error occurs

Instruction fetched from external memory

space in single chip mode

Address error occurs

Word data accessed from even address

None (normal)

Data

read/write

CPU or DTC

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

Byte or word data accessed in on-chip

peripheral module space

None (normal)

Longword data accessed in 16-bit on-chip

peripheral module space

None (normal)

Longword data accessed in 8-bit on-chip

peripheral module space

None (normal)

External memory space accessed when in

single chip mode

Address error occurs

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