SH7136 datasheet(108/1160 Pages) RENESAS

Part #	SH7136

Description	32-Bit RISC Microcomputer SuperH??RISC engine Family

PDF	1160 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 5 Exception Handling

Rev. 2.00 Sep. 10, 2008 Page 82 of 1130

REJ09B0402-0200

5.3.2

Address Error Exception Source

When an address error exception is generated, the bus cycle which caused the address error ends,

the current instruction finishes, and then the address error exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address

of the instruction which caused an address error exception. When the instruction that caused

the exception is placed in the delay slot, the address of the delayed branch instruction which is

placed immediately before the delay slot.

3. The start address of the exception handling routine is fetched from the exception handling

vector table that corresponds to the generated address error, and the program starts executing

from that address. This branch is not a delayed branch.

SH7136 Datasheet(PDF) 108 Page - Renesas Technology Corp