SH7136 datasheet(104/1160 Pages) RENESAS

104 / 1160 page

Section 5 Exception Handling

Rev. 2.00 Sep. 10, 2008 Page 78 of 1130

REJ09B0402-0200

Exception Handling Source

Vector Number

Vector Table Address Offset

Interrupt

IRQ0

H'00000100 to H'00000103

IRQ1

H'00000104 to H'00000107

IRQ2

H'00000108 to H'0000010B

IRQ3

H'0000010C to H'0000010F

(Reserved for system use)

H'00000110 to H'00000113

H'00000114 to H'00000117

H'00000118 to H'0000011B

H'0000011C to H'0000011F

On-chip peripheral module*

H'00000120 to H'00000123

255

H'000003FC to H'000003FF

Note:

For details on the vector numbers and vector table address offsets of on-chip peripheral

module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC).

Table 5.4

Calculating Exception Handling Vector Table Addresses

Exception Source

Vector Table Address Calculation

Resets

Vector table address = (vector table address offset)

= (vector number)

× 4

Address errors, interrupts,

instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Notes: 1. VBR: Vector base register

2. Vector table address offset: See table 5.3.

3. Vector number: See table 5.3.

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