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HD64F36034 Datasheet(PDF) 337 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 337 Page - Renesas Technology Corp |
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337 / 592 page ![]() Section 15 Controller Area Network for Tiny (TinyCAN) Rev. 4.00 Mar. 15, 2006 Page 305 of 556 REJ09B0026-0400 Bit Bit Name Initial Value R/W Description 6 5 4 TSG22 TSG21 TSG20 0 0 0 R/W R/W R/W Time Segment 2 This segment is used for correcting the error of 1 bit time. The TSG2 width can be set within a range of 2 to 8 time quanta. 000: Setting prohibited 001: PHSEG2 = 2 time quanta 010: PHSEG2 = 3 time quanta 011: PHSEG2 = 4 time quanta 100: PHSEG2 = 5 time quanta 101: PHSEG2 = 6 time quanta 110: PHSEG2 = 7 time quanta 111: PHSEG2 = 8 time quanta 3 2 1 0 TSG13 TSG12 TSG11 TSG10 0 0 0 0 R/W R/W R/W R/W Time Segment 1 This segment is used for absorbing the delay of the output buffer, CAN bus, and input buffer. The TSG1 width can be set within a range of 1 to 16 time quanta. TSG1 comprises PRSEG and PHSEG1 according to the CAN specifications. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: PRSEG + PHSEG1 = 4 time quanta : 1111: PRSEG + PHSEG1 = 16 time quanta |
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