HD64F36034 datasheet(340/592 Pages) RENESAS

340 / 592 page

Section 15 Controller Area Network for Tiny (TinyCAN)

Rev. 4.00 Mar. 15, 2006 Page 308 of 556

REJ09B0026-0400

15.3.8

Transmit Pending Cancel Register (TXCR)

TXCR cancels transmission of transmit pending messages in Mailboxes. By setting the TXCR bit

correspondent to TXPR, TXPR is cleared to 0. If the transmission has been canceled successfully,

the corresponding bits in both TXPR and TXCR are cleared to 0 and then the corresponding bit in

ABACK is set. Writing 0 to the bit in TXCR is ignored.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

—

Reserved

These bits are always read as 0.

MB3

MB2

MB1

R/W

[Setting condition]

The corresponding bit of a mailbox is set to 1

[Clearing condition]

When the corresponding bit in TXPR is cleared (the

transmit message is canceled successfully)

Note: Writing 1 to these bits is enabled only when the

TXPR bit corresponding to Mailbox is set to 1.

—

Reserved

This bit is always read as 0. This bit is relevant to the

receive-only Mailbox, and its value cannot be changed.

15.3.9

Transmit Acknowledge Register (TXACK)

TXACK is a status flag that indicates the successful transmit completion of Mailbox transmit

messages.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

—

Reserved

These bits are always read as 0.

MB3

MB2

MB1

R/(W)*

[Setting condition]

When transmission of the message in the corresponding

Mailbox has completed successfully

[Clearing condition]

When 1 is written to these bits

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