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HD64F36034 Datasheet(PDF) 339 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 339 Page - Renesas Technology Corp |
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339 / 592 page ![]() Section 15 Controller Area Network for Tiny (TinyCAN) Rev. 4.00 Mar. 15, 2006 Page 307 of 556 REJ09B0026-0400 15.3.7 Transmit Pending Register (TXPR) TXPR sets transmit pending (CAN bus arbitration wait) for the transmit message that is stored in a Mailbox. Setting the corresponding bit in TXPR to 1 enables a message to be transmitted. Writing 0 to the bit in TXPR is ignored. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved These bits are always read as 0. 3 2 1 MB3 MB2 MB1 0 0 0 R/W R/W R/W [Setting condition] When the corresponding MBCR bit for a mailbox is 0, the corresponding bit in TXPR is set to 1 (n = 3 to 1) [Clearing conditions] • When message transmission has completed successfully (TXACKn set) • When transmission cancellation for an untransmitted message has finished (ABACKn set) • When a transmission cancellation request has occurred during message transmission, and an error occurs or arbitration is lost on the CAN bus (ABACKn set) • When a transmit error or arbitration loss occurred with the corresponding DART bit for a message being transmitted set to 1 If the message is not transmitted successfully, the MBn bit is not cleared to 0. If any of these MB bits in TXPR are cleared to 0, the EMPI bit in TCIRR1 is set to 1. The TinyCAN automatically attempts retransmission as long as the DART bit in the message control of the corresponding Mailbox is not set to 1 or the corresponding bit in TXCR is not set to 1. Note: When the MBn bit in MBCR is set to 1, the TinyCAN does not transmit a message even if the MBn bit in TXPR is set to 1. To clear the MBn bit in TXPR to 0, set the MBn bit in TXCR to 1 beforehand. 0 — 0 — Reserved This bit is always read as 0. This bit is relevant to the receive-only Mailbox, and its value cannot be changed. |
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