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HD64F36034 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 592 page ![]() Section 12 Timer Z Rev. 4.00 Mar. 15, 2006 Page 183 of 556 REJ09B0026-0400 Bit Bit Name Initial Value R/W Description 3 IMFD 0 R/W Input Capture/Compare Match Flag D [Setting conditions] • When TCNT = GRD and GRD is functioning as output compare register • When TCNT value is transferred to GRD by input capture signal and GRD is functioning as input capture register [Clearing condition] • When 0 is written to IMFD after reading IMFD = 1 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • When TCNT = GRC and GRC is functioning as output compare register • When TCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register [Clearing condition] • When 0 is written to IMFC after reading IMFC = 1 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • When TCNT = GRB and GRB is functioning as output compare register • When TCNT value is transferred to GRB by input capture signal and GRB is functioning as input capture register [Clearing condition] • When 0 is written to IMFB after reading IMFB = 1 |
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