HD64F36034 datasheet(213/592 Pages) RENESAS

213 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 181 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

IOA2

IOA1

IOA0

R/W

I/O Control A2 to A0

GRA is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRA compare match

010: 1 output by GRA compare match

011: Toggle output by GRA compare match

GRA is an input capture register:

100: Input capture to GRA at the rising edge

101: Input capture to GRA at the falling edge

11X: Input capture to GRA at both rising and falling edges

[Legend]

X: Don't care

TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input

capture register. When an output compare register is selected, the output setting is selected. When

an input capture register is selected, an input edge of an input capture signal is selected. TIORC

also selects the function of FTIOC or FTIOD pin.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 1.

IOD2

IOD1

IOD0

R/W

I/O Control D2 to D0

GRD is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRD compare match

010: 1 output by GRD compare match

011: Toggle output by GRD compare match

GRD is an input capture register:

100: Input capture to GRD at the rising edge

101: Input capture to GRD at the falling edge

11X: Input capture to GRD at both rising and falling edges



Reserved

This bit is always read as 1.

HD64F36034 Datasheet(PDF) 213 Page - Renesas Technology Corp

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