HD64F36034 datasheet(209/592 Pages) RENESAS

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Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 177 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

TOA1

R/W

Output Level Select A1

0: 0 output at the FTIOA1 pin*

1: 1 output at the FTIOA1 pin*

TOD0

R/W

Output Level Select D0

0: 0 output at the FTIOD0 pin*

1: 1 output at the FTIOD0 pin*

TOC0

R/W

Output Level Select C0

0: 0 output at the FTIOC0 pin*

1: 1 output at the FTIOC0 pin*

TOB0

R/W

Output Level Select B0

0: 0 output at the FTIOB0 pin*

1: 1 output at the FTIOB0 pin*

TOA0

R/W

Output Level Select A0

0: 0 output at the FTIOA0 pin*

1: 1 output at the FTIOA0 pin*

Note:

The change of the setting is immediately reflected in the output value.

12.3.7

Timer Counter (TCNT)

The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT

counters are 16-bit readable/writable registers that increment/decrement according to input clocks.

Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1

increment/decrement in complementary PWM mode, while they only increment in other modes.

The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB,

GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When

the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When

TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8-

bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000.

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