HD64F36034 datasheet(210/592 Pages) RENESAS

210 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 178 of 556

REJ09B0026-0400

12.3.8

General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)

GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR

registers are dual function 16-bit readable/writable registers, functioning as either output compare

or input capture registers. Functions can be switched by TIORA and TIORC.

The values in GR and TCNT are constantly compared with each other when the GR registers are

used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR

are set to 1. Compare match outputs can be selected by TIORA and TIORC.

When the GR registers are used as input capture registers, the TCNT value is stored after detecting

external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1.

Detection edges for input capture signals can be selected by TIORA and TIORC.

When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the

values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare

registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units;

they must always be accessed as a 16-bit unit.

HD64F36034 Datasheet(PDF) 210 Page - Renesas Technology Corp