HD64F36034 datasheet(212/592 Pages) RENESAS

212 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 180 of 556

REJ09B0026-0400

12.3.10

Timer I/O Control Register (TIORA and TIORC)

The TIOR registers control the general registers (GR). Timer Z has four TIOR registers

(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including

complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.

TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input

capture register. When an output compare register is selected, the output setting is selected. When

an input capture register is selected, an input edge of an input capture signal is selected. TIORA

also selects the function of FTIOA or FTIOB pin.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 1.

IOB2

IOB1

IOB0

R/W

I/O Control B2 to B0

GRB is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRB compare match

010: 1 output by GRB compare match

011: Toggle output by GRB compare match

GRB is an input capture register:

100: Input capture to GRB at the rising edge

101: Input capture to GRB at the falling edge

11X: Input capture to GRB at both rising and falling edges



Reserved

This bit is always read as 1.

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