HD64F36034 datasheet(208/592 Pages) RENESAS

208 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 176 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

EC0

R/W

Master Enable C0

0: FTIOC0 pin output is enabled according to the TPMR,

TFCR, and TIORC_0 settings

1: FTIOC0 pin output is disabled regardless of the TPMR,

TFCR, and TIORC_0 settings (FTIOC0 pin is operated

as an I/O port).

EB0

R/W

Master Enable B0

0: FTIOB0 pin output is enabled according to the TPMR,

TFCR, and TIORA_0 settings

1: FTIOB0 pin output is disabled regardless of the TPMR,

TFCR, and TIORA_0 settings (FTIOB0 pin is operated

as an I/O port).

EA0

R/W

Master Enable A0

0: FTIOA0 pin output is enabled according to the TPMR,

TFCR, and TIORA_0 settings

1: FTIOA0 pin output is disabled regardless of the TPMR,

TFCR, and TIORA_0 settings (FTIOA0 pin is operated

as an I/O port).

12.3.6

Timer Output Control Register (TOCR)

TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits

OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and

complementary PWM mode.

Bit

Bit Name

Initial

Value

R/W

Description

TOD1

R/W

Output Level Select D1

0: 0 output at the FTIOD1 pin*

1: 1 output at the FTIOD1 pin*

TOC1

R/W

Output Level Select C1

0: 0 output at the FTIOC1 pin*

1: 1 output at the FTIOC1 pin*

TOB1

R/W

Output Level Select B1

0: 0 output at the FTIOB1 pin*

1: 1 output at the FTIOB1 pin*

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