HD64F36034 datasheet(214/592 Pages) RENESAS

214 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 182 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

value

R/W

Description

IOC2

IOC1

IOC0

R/W

I/O Control C2 to C0

GRC is an output compare register:

000: Disables pin output by compare match

001: 0 output by GRC compare match

010: 1 output by GRC compare match

011: Toggle Output by GRC compare match

GRC is an input capture register:

100: Input capture to GRC at the rising edge

101: Input capture to GRC at the falling edge

11X: Input capture to GRC at both rising and falling edges

[Legend]

X: Don't care

12.3.11

Timer Status Register (TSR)

TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture

of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a

corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,

one for each channel.

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 1



Reserved

These bits are always read as 1.

UDF*

R/W

Underflow Flag

[Setting condition]

• When TCNT_1 underflows

[Clearing condition]

• When 0 is written to UDF after reading UDF = 1

OVF

R/W

Overflow Flag

[Setting condition]

• When the TCNT value underflows

[Clearing condition]

• When 0 is written to OVF after reading OVF = 1

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