HD64F36022 datasheet(53/384 Pages) RENESAS

Part #	HD64F36022

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

PDF	384 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 2 CPU

Rev. 4.00 Sep. 23, 2005 Page 27 of 354

REJ09B0025-0400

Table 2.8

System Control Instructions

Instruction

Size*

Function

TRAPA

—

Starts trap-instruction exception handling.

RTE

—

Returns from an exception-handling routine.

SLEEP

—

Causes a transition to a power-down state.

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the CCR. The CCR size is one

byte, but in transfer from memory, data is read by word access.

STC

B/W

CCR

→ (EAd), EXR → (EAd)

Transfers the CCR contents to a destination location. The condition

code register size is one byte, but in transfer to memory, data is written

by word access.

ANDC

CCR

∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR with immediate data.

ORC

CCR

∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR with immediate data.

XORC

CCR

⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically XORs the CCR with immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note:

Refers to the operand size.

B: Byte

W: Word

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