HD64F36022 datasheet(86/384 Pages) RENESAS

86 / 384 page

Section 4 Address Break

Rev. 4.00 Sep. 23, 2005 Page 60 of 354

REJ09B0025-0400

• Break data register (BDRH, BDRL)

4.1.1

Address Break Control Register (ABRKCR)

ABRKCR sets address break conditions.

Bit

Bit Name

Initial

Value

R/W

Description

RTINTE

R/W

RTE Interrupt Enable

When this bit is 0, the interrupt immediately after

executing RTE is masked and then one instruction must

be executed. When this bit is 1, the interrupt is not

masked.

CSEL1

CSEL0

R/W

Condition Select 1 and 0

These bits set address break conditions.

00: Instruction execution cycle

01: CPU data read cycle

10: CPU data write cycle

11: CPU data read/write cycle

ACMP2

ACMP1

ACMP0

R/W

Address Compare Condition Select 2 to 0

These bits comparison condition between the address set

in BAR and the internal address bus.

000: Compares 16-bit addresses

001: Compares upper 12-bit addresses

010: Compares upper 8-bit addresses

011: Compares upper 4-bit addresses

1XX: Reserved (setting prohibited)

DCMP1

DCMP0

R/W

Data Compare Condition Select 1 and 0

These bits set the comparison condition between the data

set in BDR and the internal data bus.

00: No data comparison

01: Compares lower 8-bit data between BDRL and data

bus

10: Compares upper 8-bit data between BDRH and data

bus

11: Compares 16-bit data between BDR and data bus

Legend: X: Don't care.

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