HD64F36022 datasheet(54/384 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Sep. 23, 2005 Page 28 of 354

REJ09B0025-0400

Table 2.9

Block Data Transfer Instructions

Instruction

Size

Function

EEPMOV.B

—

if R4L

≠ 0 then

Repeat @ER5+

→ @ER6+,

R4L–1

→ R4L

Until R4L = 0

else next;

EEPMOV.W

—

if R4

≠ 0 then

Repeat @ER5+

→ @ER6+,

R4–1

→ R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set

in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

2.4.2

Basic Instruction Formats

H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op field), a register field (r field), an effective address extension (EA field), and a

condition field (cc).

Figure 2.7 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3

bits or 4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit

address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).

• Condition Field

Specifies the branching condition of Bcc instructions.

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