HD64F36022 datasheet(91/384 Pages) RENESAS

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Section 5 Clock Pulse Generators

CPG0200A_000020020200

Rev. 4.00 Sep. 23, 2005 Page 65 of 354

REJ09B0025-0400

Section 5 Clock Pulse Generators

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system

clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a

duty correction circuit, and system clock dividers.

Figure 5.1 shows a block diagram of the clock pulse generators.

System

clock

oscillator

Duty

correction

circuit

System

clock

divider

Prescaler S

(13 bits)

OSC1

OSC2

System clock pulse generator

φOSC

(fOSC)

φOSC

(fOSC)

φ/2

φ/8192

φOSC/8

φOSC

φOSC/16

φOSC/32

φOSC/64

Figure 5.1 Block Diagram of Clock Pulse Generators

The basic clock signals that drive the CPU and on-chip peripheral modules are system clocks (

φ).

The system clock is divided into

φ/8192 to φ/2 by prescaler S and they are supplied to respective

peripheral modules.

5.1

System Clock Generator

Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic

resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system

clock generator.

LPM

LPM: Low-power mode (standby mode, subsleep mode)

OSC

Figure 5.2 Block Diagram of System Clock Generator

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