HD64F36022 datasheet(79/384 Pages) RENESAS

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Section 3 Exception Handling

Rev. 4.00 Sep. 23, 2005 Page 53 of 354

REJ09B0025-0400

3.4

Interrupt Exception Handling

3.4.1

External Interrupts

There are external interrupts, NMI, IRQ3, IRQ0, and WKP.

(1)

NMI

NMI interrupt is requested by input falling edge to pin

NMI.

NMI is the highest interrupt, and can always be accepted without depending on the I bit value in

CCR.

(2)

IRQ3 to IRQ0 Interrupts

IRQ3 to IRQ0 interrupts are requested by input signals to pins

IRQ3 to IRQ0. These four

interrupts are given different vector addresses, and are detected individually by either rising edge

sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.

When pins

IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal

edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. When

IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by

setting bits IEN3 to IEN0 in IENR1.

(3)

WKP5 to WKP0 Interrupts

WKP5 to WKP0 interrupts are requested by input signals to pins

WKP5 to WKP0. These six

interrupts have the same vector addresses, and are detected individually by either rising edge

sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.

When pins

WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal

edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These

interrupts can be masked by setting bit IENWP in IENR1.

HD64F36022 Datasheet(PDF) 79 Page - Renesas Technology Corp