| Electronic Components Datasheet Search |
|
HD64F36022 Datasheet(PDF) 73 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F36022 Datasheet(HTML) 73 Page - Renesas Technology Corp |
|
73 / 384 page ![]() Section 3 Exception Handling Rev. 4.00 Sep. 23, 2005 Page 47 of 354 REJ09B0025-0400 3.2 Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt flag register 1 (IRR1) • Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and IRQ0. Bit Bit Name Initial Value R/W Description 7 0 − Reserved This bit is always read as 0. 6 to 4 All 1 Reserved These bits are always read as 1. 3 IEG3 0 R/W IRQ3 Edge Select 0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected 2, 1 All 0 Reserved These bits are always read as 0. 0 IEG0 0 R/W IRQ0 Edge Select 0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |