HD64F36022 datasheet(88/384 Pages) RENESAS

88 / 384 page

Section 4 Address Break

Rev. 4.00 Sep. 23, 2005 Page 62 of 354

REJ09B0025-0400

4.1.3

Break Address Registers (BARH, BARL)

BARH and BARL are 16-bit read/write registers that set the address for generating an address

break interrupt. When setting the address break condition to the instruction execution cycle, set

the first byte address of the instruction. The initial value of this register is H'FFFF.

4.1.4

Break Data Registers (BDRH, BDRL)

BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break

interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-

bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for

even and odd addresses in the data transmission. Therefore, comparison data must be set in

BDRH for byte access. For word access, the data bus used depends on the address. See section

4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is

undefined.

4.2

Operation

When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an

interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the

address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt

request is accepted, interrupt exception handling starts after the instruction being executed ends.

The address break interrupt is not masked because of the I bit in CCR of the CPU.

HD64F36022 Datasheet(PDF) 88 Page - Renesas Technology Corp