HD64F36022 datasheet(82/384 Pages) RENESAS

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Section 3 Exception Handling

Rev. 4.00 Sep. 23, 2005 Page 56 of 354

REJ09B0025-0400

PC and CCR

saved to stack

SP (R7)

SP – 1

SP – 2

SP – 3

SP – 4

Stack area

SP + 4

SP + 3

SP + 2

SP + 1

SP (R7)

Even address

Prior to start of interrupt

exception handling

After completion of interrupt

exception handling

Legend:

PCH :

PCL :

CCR:

SP:

Upper 8 bits of program counter (PC)

Lower 8 bits of program counter (PC)

Condition code register

Stack pointer

Notes:

CCR

CCR*3

PCH

PCL

PC shows the address of the first instruction to be executed upon return from the interrupt

handling routine.

an even-numbered address.

3. Ignored when returning from the interrupt handling routine.

Figure 3.2 Stack Status after Exception Handling

3.4.4

Interrupt Response Time

Table 3.2 shows the number of wait states after an interrupt request flag is set until the first

instruction of the interrupt handling-routine is executed.

Table 3.2

Interrupt Wait States

Item

States

Total

Waiting time for completion of executing instruction*

1 to 23

15 to 37

Saving of PC and CCR to stack

Vector fetch

Instruction fetch

Internal processing

Note:

Not including EEPMOV instruction.

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