HD64F36022 datasheet(173/384 Pages) RENESAS

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Section 11 Timer W

Rev. 4.00 Sep. 23, 2005 Page 147 of 354

REJ09B0025-0400

11.3.7

Timer Counter (TCNT)

TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to

CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting

the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF

flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is

generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.

TCNT is initialized to H'0000 by a reset.

11.3.8

General Registers A to D (GRA to GRD)

Each general register is a 16-bit readable/writable register that can function as either an output-

compare register or an input-capture register. The function is selected by settings in TIOR0 and

TIOR1.

When a general register is used as an input-compare register, its value is constantly compared with

the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA,

IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when

IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR.

When a general register is used as an input-capture register, an external input-capture signal is

detected and the current TCNT value is stored in the general register. The corresponding flag

(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit

(IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is

generated. The edge of the input-capture signal is selected in TIOR.

GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA

and BUFEB in TMRW.

For example, when GRA is set as an output-compare register and GRC is set as the buffer register

for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is

generated.

When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the

value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to

GRA whenever an input capture is generated.

GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are

initialized to H'FFFF by a reset.

HD64F36022 Datasheet(PDF) 173 Page - Renesas Technology Corp