32186 datasheet(437/1032 Pages) RENESAS

437 / 1032 page

MULTIJUNCTION TIMERS

10-141

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.7.6 Outline of Each Mode of TID

Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time.

(1) Fixed period count mode

In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of

" reload register set value + 1."

Note: • TINn cannot be used as a clock source.

When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initial

value being undefined), the counter is loaded with the content of " the reload register -1" and starts counting

synchronously with the count clock at the next cycle. The counter counts down and when it underflows after

reaching the minimum count, the counter is loaded with the content of " the reload register -1" and continues

counting. To stop the counter, disable count by writing to the enable bit in software. An interrupt request and

a DMA transfer request can be generated each time the counter underflows.

The " reload register set value + 1" is effective as count value.

H'(E000-1)

Count clock

Counter

Enabled

(by writing to the enable bit)

Underflow

(first time)

TID0 interrupt request

due to underflow

Enable bit

Reload register

Underflow

(second time)

Undefined

value

DMA transfer request

due to underflow

(Note 1)

Note 1: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

(Note 1)

H'FFFF

H'0000

H'E000

H'(E000-1)

H'E000

Counter

Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode

10.7 TID (Input-Related 16-Bit Timer)

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