32186 datasheet(445/1032 Pages) RENESAS

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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-149

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

BCLK

Count clock

Enable

F/F operation (Note 1)

Count clock period

Count clock-dependent

delay

Write to the enable bit

Note 1: This applies to the case where F/F output is inverted when the timer is enabled.

Inverted

Figure 10.8.2 Count Clock Dependent Delay

(4) Single-shot output mode (without correction function)

In single-shot output mode, the timer generates a pulse in width of " reload register set value + 1" only once

and then stops.

When the timer is enabled after setting the reload register, the counter is loaded with the content of " the

reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter

counts down and when the minimum count is reached, stops upon underflow.

The F/F output waveform in single-shot output mode is inverted (F/F output level changes from "L" to "H" or

vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of " reload

counter underflows.

(5) Continuous output mode (without correction function)

In continuous output mode, the timer counts down starting from the set value of the counter and when the

counter underflows, it is loaded with the value that the reload register. Thereafter, this operation is repeated

each time the counter underflows, thus generating inverted consecutive pulses in width of " reload register

set value + 1."

When the timer is enabled after setting the counter and reload register, it starts counting down from the

counter’s set value synchronously with the count clock and when the minimum count is reached, generates

an underflow. At the cycle after this underflow causes the counter to be loaded with the content of " the

reload register -1" and start counting over again at the next cycle. Thereafter, this operation is repeated

each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software.

The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or

vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer

stops counting. An interrupt request and DMA transfer request can be generated each time the counter

underflows.

• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay

is generated by the time when the timer actually starts operating after writing the enable bit. In operation

mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent

delay before the F/F output is inverted.

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