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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-161

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(2) TOU reload registers during PWM output and single-shot PWM output modes

TOU0_0 Reload 0 Register (TOU00RL0)

<Address: H'0080 0796>

TOU0_1 Reload 0 Register (TOU01RL0)

<Address: H'0080 079E>

TOU0_2 Reload 0 Register (TOU02RL0)

<Address: H'0080 07A6>

TOU0_3 Reload 0 Register (TOU03RL0)

<Address: H'0080 07AE>

TOU0_4 Reload 0 Register (TOU04RL0)

<Address: H'0080 07B6>

TOU0_5 Reload 0 Register (TOU05RL0)

<Address: H'0080 07BE>

TOU0_6 Reload 0 Register (TOU06RL0)

<Address: H'0080 07C6>

TOU0_7 Reload 0 Register (TOU07RL0)

<Address: H'0080 07CE>

TOU1_0 Reload 0 Register (TOU10RL0)

<Address: H'0080 0B96>

TOU1_1 Reload 0 Register (TOU11RL0)

<Address: H'0080 0B9E>

TOU1_2 Reload 0 Register (TOU12RL0)

<Address: H'0080 0BA6>

TOU1_3 Reload 0 Register (TOU13RL0)

<Address: H'0080 0BAE>

TOU1_4 Reload 0 Register (TOU14RL0)

<Address: H'0080 0BB6>

TOU1_5 Reload 0 Register (TOU15RL0)

<Address: H'0080 0BBE>

TOU1_6 Reload 0 Register (TOU16RL0)

<Address: H'0080 0BC6>

TOU1_7 Reload 0 Register (TOU17RL0)

<Address: H'0080 0BCE>

Bit Name

Function

0–15

TOU00RL0–TOU07RL0,

16-bit reload register value

TOU10RL0–TOU17RL0

Note: • These registers must always be accessed in halfwords.

During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 0

The content of " the reload 0 register -1" is loaded into the counter synchronously with the count clock at the

following timing:

• At the next cycle when the counter is enabled

• At the next cycle when the count value set in the reload 1 register has underflowed in PWM output mode

Simply because data is written to the reload register does not mean that the data is loaded into the counter. The

counter is loaded with data in only the above cases.

If the value ‘H'FFFF’ is set in the reload register, F/F output will not be inverted, making it possible to produce

a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output

during PWM Output and Single-shot PWM Output Modes.”

During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1

registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU

reload registers during single-shot output, delayed single-shot output and continuous output modes.”

b15

TOU00RL0–TOU07RL0, TOU10RL0–TOU17RL0

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