32186 datasheet(454/1032 Pages) RENESAS

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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-158

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or

continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence

of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the

count clock. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respec-

tively. Bits 0–7 are ignored.

When writing to the counter separately in high and low-order bits, rewrite the 8 high-order bits first and then the

16 low-order bits. The 8 high-order bits become effective when the 16 low-order bits are rewritten. If the counter

is rewritten in the reverse order beginning with the 16 low-order bits, the value of the 8 high-order bits is not

reflected until the next time the 16 low-order bits are rewritten. If the 8 high-order bits are read before the CPU

has finished rewriting the 16 low-order bits after rewriting the 8 high-order bits. The read value shows the

previous data (when not counting) or the current count of the previous data (when count is in progress), and not

the new rewritten data. If the counter is written to in 32-bit units, it is rewritten successively in order of the 8

high-order bits and then the 16 low-order bits automatically.

During PWM output or single-shot PWM output mode, the TOU counters operate as a 16-bit down-counter

where only the 16 low-order bits are effective. For details, see Section 10.8.6, Paragraph (2), “TOU counters

during PWM output and single-shot PWM output modes.”

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