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32186 Datasheet(PDF) 460 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 460 Page - Renesas Technology Corp |
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460 / 1032 page ![]() 10.8 TOU (Output-Related 24-Bit Timer) MULTIJUNCTION TIMERS 10 10-164 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 b8 9 10 11121314 b15 TOUn0CEN TOUn1CEN TOUn2CEN TOUn3CEN TOUn4CEN TOUn5CEN TOUn6CEN TOUn7CEN 000 0000 0 10.8.9 TOU Count Enable Registers TOU0 Count Enable Register (TOU0CEN) <Address: H’0080 07DF> TOU1 Count Enable Register (TOU1CEN) <Address: H'0080 0BDF> <Upon exiting reset: H’00> b Bit Name Function R W 8 TOUn0CEN 0: Stop count R W TOUn_0 count enable bit 1: Enable count 9 TOUn1CEN TOUn_1 count enable bit 10 TOUn2CEN TOUn_2 count enable bit 11 TOUn3CEN TOUn_3 count enable bit 12 TOUn4CEN TOUn_4 count enable bit 13 TOUn5CEN TOUn_5 count enable bit 14 TOUn6CEN TOUn_6 count enable bit 15 TOUn7CEN TOUn_7 count enable bit The TOU count enable registers control operation of the TOU counters. To enable any TOU counter in soft- ware, enable its corresponding enable protect bit for rewrite and set the count enable bit by writing "1." To stop any TOU counter, enable its corresponding enable protect bit for rewrite and reset the count enable bit by writing "0." In single-shot output, single-shot PWM output or delayed single-shot output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TOU count enable register when accessed for read serves as a status register indicating whether the counter is operating or idle. |
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