32186 datasheet(464/1032 Pages) RENESAS

464 / 1032 page

10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-168

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.8.11 PWM Output Disable Control Registers

PWM Output 0 Disable Control Register GA (PO0DISGACR)

<Address: H’0080 0520>

Bit Name

Function

0–5

No function assigned. Fix to "0."

PO0DISGAP

–

PO0DISGA write control bit

PO0DISGA

0: Enable output

P87/TO21–P82/TO26 output disable select bit

1: Disable output

PWM Output 1 Disable Control Register GA (PO1DISGACR)

<Address: H'0080 0522>

Bit Name

Function

0–5

No function assigned. Fix to "0."

PO1DISGAP

–

PO1DISGA write control bit

PO1DISGA

0: Enable output

P110/TO29–P115/TO34 output disable select bit

1: Disable output

PWM Output 0 Disable Control Register GB (PO0DISGBCR)

<Address: H’0080 0780>

Bit Name

Function

0–5

No function assigned. Fix to "0."

PO0DISGBP

–

PO0DISGB write control bit

PO0DISGB

0: Enable output

P00/TO21–P05/TO26 output disable select bit

1: Disable output

3456

PO0DISGAP PO0DISGA

000

0000

3456

PO1DISGAP PO1DISGA

000

0000

3456

PO0DISGBP PO0DISGB

000

0000

PWM output disable control register is a register which performs disable control of the PWM output from TO

21–26 and TO29–TO34 terminal. Refer to the "10.8.20 PWM Output Disable Function" for the details of PWM

Output Disable Function.

The procedure of setting up a POnDISGm bit is described blow.

1. Set POnDISGmP Bit of POnDISGmCR as "1" and write it.

2. Write "0" in POnDISGmP Bit and write setting value in POnDISGm Bit.

Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2,

the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the

writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting.

However the writing cycle from RTD and DRI are not effected.

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