32186 datasheet(471/1032 Pages) RENESAS

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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-175

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 10.8.7 Typical Operation in PWM Output Mode

H'A000

H'(A000-1)

H'C000

H'A000

H'(A000-1)

Count clock

Enabled

(by writing to the enable bit

or by external input)

Underflow

(first time)

Enable bit

Reload 0 register

Underflow

(second time)

Reload 1 register

Reload 1 buffer

Undefined

value

(Note 2)

DMA transfer request

F/F output (Note 4)

Interrupt request

due to underflow

One count clock equivalent delay

Note 1: The value that "reload 0 register - 1" is reloaded.

Note 2: The value that "reload 1 buffer - 1" is reloaded.

Note 3: When reload0 is reloaded after updating reload0 register, reload 1 buffer is tranferd.

Note 4: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform

that is outputting at present.

Updating is reflected at the next PWM period after updating reload 0 register.

Note: • This diagram does not show detailed timing information.

(Note 1)

H'FFFF

H'0000

H'A000

H'(C000-1)

H'C000

H'A000

Counter

Count down from the

reload 0 register

set value

Count down from the

reload 1 register

set value

Data inverted

by enable

Data inverted

by underflow

Data inverted

by underflow

PWM output period

One count clock equivalent delay

(Note 3)

Count down from the

reload 0 register

set value

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