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32186 Datasheet(PDF) 524 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 524 Page - Renesas Technology Corp |
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524 / 1032 page ![]() 11 A/D CONVERTER 11-26 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 11.2.6 A/D Conversion Speed Control Register A/D0 Conversion Speed Control Register (AD0CVSCR) <Address: H’0080 0087> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00 14 ADCVSD2 (Note 1) 0: 2BCLK mode R W A/D conversion speed control bit 2 1: BCLK mode 15 ADCVSD (Note 1) 0: Slow mode R W A/D conversion speed control bit 1: Fast mode Note 1: The A/D conversion speed is determined by a combination of AD0CVSD and AD0CVSD2 bits and A/D0 Single Mode Register 1’s ADSSPD bit during single mode, or a combination of AD0CVSD and AD0CVSD2 bits and A/D Scan Mode Register 1’s ADCSPD bit during scan mode. The A/D Conversion Speed Control Register controls the A/D conversion speed during single and scan modes of the A/D Converter. The A/D conversion speed is determined in combination with the conversion speed select bits (Double/Normal) in A/D Single Mode Register 1 and A/D Scan Mode Register 1. b8 9 10 11121314 b15 ADCVSD2 ADCVSD 0000000 0 11.2 A/D Converter Related Registers |
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