32186 datasheet(546/1032 Pages) RENESAS

546 / 1032 page

A/D CONVERTER

11-48

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Thus, for a 10-bit resolution A/D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value

for reference when setting up C1.

(b) Maximum value of the output impedance R1 when C1 is not added

If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the

analog output device can fully charge C2 within a predetermined time. First, the equation to find i2

when C1 in Figure 11.5.1 does not exist is shown below.

i2 =

C2(E - V2)

×exp

{

- t

}

------------------------ Eq. B-1

Cin

× R1+ C2(R1+R2)

Cin

×R1+C2(R1+R2)

11.5 Notes on Using A/D Converter

(a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended)

Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the

internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance divi-

sion of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have. For a 10-

bit A/D Converter where VREF0 is 5.12 V, 1 LSB determination voltage = 5.12 V/1,024 = 5 mV. The

potential fluctuation of 0.1 LSB means a 0.5 mV fluctuation.

Vp is also obtained by the equation below:

The relationship between the capacitance division of C1 and C2 and the potential fluctuation,

Vp, is obtained by the equation below:

C1 + C2

Vp =

× (E - V2)

Eq. A-1

Vp = Vp1

Eq. A-2

VREF0

× 2×

x - 1

∑

i = 0

where Vp1 = potential fluctuation in the first A/D conversion performed

and x = 10 for a 10-bit resolution A/D converter

When Eq. A-1 and Eq. A-2 are solved, the following results:

E - V2

Vp1

C1 = C2 {

- 1 }

Eq. A-3

∴ C1 > C2 {10 × 2×

- 1 }

Eq. A-4

x - 1

∑

i = 0

ADiINn

Conversion time

for the first bit

Sampling time

Comparison

time

Repeated (10 times) for 10 bits

Second bit

Sampling time

When sample-and-hold

is disabled

* When sample-and-hold is enabled, the analog input is sampled for only the first bit.

Figure 11.5.2 A/D Conversion Timing Diagram

Figure 11.5.2 shows an A/D conversion timing diagram. C2 must be charged up within the sampling

time shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the

second and subsequent bits is about half that of the first bit.

The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when

the sample-and-hold function is enabled, the analog input is sampled for only the first bit.

32186 Datasheet(PDF) 546 Page - Renesas Technology Corp

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