32186 datasheet(550/1032 Pages) RENESAS

550 / 1032 page

SERIAL INTERFACE

12-2

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.1 Outline of Serial Interface

The 32185/32186 contains a total of six serial interface channels, SIO0–SIO5. Channels SIO0, SIO1, SIO4

and SIO5 can be selected between CSIO mode (clock-synchronous serial interface) and UART mode (clock-

asynchronous serial interface). Channels SIO2 and SIO3 are UART mode only.

• CSIO mode (clock-synchronous serial interface)

Communication is performed synchronously with a transfer clock, using the same clock on both trans-

mit and receive sides. The transfer data length can be selected within the range from 8 to 16 bits long.

• UART mode (clock-asynchronous serial interface)

Communication is performed at any transfer rate in any transfer data format. The transfer data length

can be selected from 7, 8 and 9 bits.

Channels SIO0–SIO5 each have a transmit DMA transfer and a receive DMA transfer request. These

serial interfaces, when combined with the internal DMA Controller (DMAC), allow serial communica-

tion to be performed at high speed, as well as reduce the data communication load of the CPU.

Serial interface is outlined below.

Table 12.1.1 Outline of Serial interface

Item

Description

Number of channels

CSIO mode and UART mode

: 4 channels (SIO0, SIO1, SIO4, SIO5)

UART only

: 2 channels (SIO2, SIO3)

Clock

During CSIO mode : Internal clock or external clock as selected (Note 1), clock polarity can be selected

During UART mode : Internal clock only

Transfer mode

Transmit half-duplex, receive half-duplex, transmit/receive full-duplex

BRG count source

f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2)

(when internal clock selected)

f(BCLK)/2, f(BCLK)/16, f(BCLK)/64, f(BCLK)/512

f(BCLK): Peripheral clock operating frequency

Data format

CSIO mode

: Data length = selectable in the range of 8–16 bits

Order of transfer = selectable from LSB first or MSB first

UART mode

: Start bit = 1 bit

Character length = 7, 8 or 9 bits

Parity bit = Added (odd, even) or not added

Stop bit = 1 or 2 bits

Order of transfer = selectable from LSB first or MSB first

Baud rate

CSIO mode

: 76 bits/sec to 2.5 Mbits/sec (when f(BCLK) = 20 MHz/internal clock selected)

Max 1.25 Mbits/sec (when f(BCLK) = 20 MHz/external clock selected)

UART mode

: 9.5 bits/sec to 1.25 Mbits/sec (when f(BCLK) = 20 MHz)

Error detection

CSIO mode

: Overrun error only

UART mode

: Overrun, parity and framing errors

(Occurrence of any of these errors is indicated by an error sum bit)

Fixed period clock

When using SIO0, SIO1, SIO4 and SIO5 as UART mode, this function outputs a divided-by-2

BRG output function

clock from the SCLK pin.

Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16.

Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.

12.1 Outline of Serial Interface

32186 Datasheet(PDF) 550 Page - Renesas Technology Corp

32186 Datasheet(HTML) 550 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL