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32186 Datasheet(PDF) 552 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 552 Page - Renesas Technology Corp |
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552 / 1032 page  SERIAL INTERFACE 12 12-4 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 SCLKI4/SCLKO4 To DMA0 Receive DMA transfer request Transmit DMA transfer request To DMA1 SCLKI0/SCLKO0 Baud Rate Generator (BRG) CSIO mode When internal clock selected CSIO mode UART mode When internal clock selected 1/16 1/2 RXD0 TXD0 Receive interrupt request Transmit/ Receive Control Circuit SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To DMA3, DMA4 SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock selected When UART mode selected SCLKI1/SCLKO1 To DMA6 To the Interrupt Controller (ICU) SIO0 SIO1 SIO2 SIO3 RXD1 TXD1 Transmit/ Receive Control Circuit SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA7 RXD2 TXD2 Transmit/ Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register To DMA7, DMA9 RXD3 TXD3 Transmit/ Receive Control Circuit SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To the Interrupt Controller (ICU) To DMA8 To DMA5 To DMA3, DMA6 To DMA4 SIO4 RXD4 TXD4 Transmit/ Receive Control Circuit SIO4 Transmit Shift Register SIO4 Receive Shift Register Receive interrupt request Transmit interrupt request To the Interrupt Controller (ICU) To the Interrupt Controller (ICU) Notes: • When f(BCLK) is selected as BRG count source, the BRG set value is subject to limitations. • SIO2 and SIO3 do not have the SCLKI/SCLKO function. SIO5 RXD5 TXD5 Transmit/ Receive Control Circuit SIO5 Transmit Shift Register SIO5 Receive Shift Register Receive interrupt request Transmit interrupt request BCLK 1/2 Clock Divider 1/1 1/8 1/32 1/256 SCLKI5/SCLKO5 To DMA2 Receive DMA transfer request Transmit DMA transfer request To DMA3 Figure 12.1.1 Block Diagram of Serial Interfaces 12.1 Outline of Serial Interface |
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