32186 datasheet(556/1032 Pages) RENESAS

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SERIAL INTERFACE

12-8

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Receive

DMA transfer request

RFIN

(Reception Finished bit)

Note: • No reception-finished DMA transfer requests are generated if a receive error occurs.

Figure 12.2.4 Reception-finished DMA Transfer Request

(3) Selecting the source of an interrupt request

The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are broadly

classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be gener-

ated when the transmit buffer is empty or transmission is finished, and the receive interrupt re-

quests can be generated when reception is finished or an receive error is detected, as selected by

the Interrupt Request Source Select Registers (SI03SEL, SI45SEL).

Notes: • No interrupt request signals are generated unless interrupts are generated by the SIO

Interrupt Request Mask Register after enabling the TEN (Transmit Enable) bit or REN

(Receive Enable) bit for the corresponding SIO.

• SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5.

• The transmission-finished interrupt is effective when the internal clock is selected in UART

or CSIO mode.

(4) Notes on using transmit interrupts

When the interrupt request is enable in SIO Interrupt Request Mask Register and the transmit

buffer empty interrupt is selected in SIO Interrupt Request Source Select Register, a transmit

interrupt request is generated upon enabling the corresponding TEN (Transmit Enable) bit.

(5) About DMA transfer requests from SIO

Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request.

These DMA transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit

Enable) bit or REN (Receive Enable) bit. When using DMA transfers to communicate with external

devices, be sure to set the DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-

finished DMA transfer requests are generated if a receive error occurs.

• Transmit DMA transfer request

Generated when the transmit buffer is empty and the TEN bit is enabled.

TEN

(Transmit Enable bit)

TBE

(Transmit Buffer

Empty bit)

Transmit DMA

transfer request

Figure 12.2.3 Transmit DMA Transfer Request

• Reception-finished DMA transfer request

A DMA transfer request is generated when the receive buffer is filled.

12.2 Serial Interface Related Registers

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