32186 datasheet(557/1032 Pages) RENESAS

557 / 1032 page

SERIAL INTERFACE

12-9

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

SIO23 Interrupt Request Status Register (SI23STAT)

<Address: H’0080 0100>

123456

IRQT2

IRQR3

IRQT3

IRQR2

0000

Bit Name

Function

0–3

No function assigned. Fix to "0."

IRQT2

0: Interrupt not requested

R (Note 1)

SIO2 transmit interrupt request status bit

1: Interrupt requested

IRQR2

0: Interrupt not requested

R (Note 1)

SIO2 receive interrupt request status bit

1: Interrupt requested

IRQT3

0: Interrupt not requested

R (Note 1)

SIO3 transmit interrupt request status bit

1: Interrupt requested

IRQR3

0: Interrupt not requested

R (Note 1)

SIO3 receive interrupt request status bit

1: Interrupt requested

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

SIO45 Interrupt Request Status Register (SI45STAT)

<Address: H’0080 0A00>

123456

IRQT4

IRQR5

IRQT5

IRQR4

0000

Bit Name

Function

IRQT4

0: Interrupt not requested

R (Note 1)

SIO4 transmit interrupt request status bit

1: Interrupt requested

IRQR4

0: Interrupt not requested

R (Note 1)

SIO4 receive interrupt request status bit

1: Interrupt requested

IRQT5

0: Interrupt not requested

R (Note 1)

SIO5 transmit interrupt request status bit

1: Interrupt requested

IRQR5

0: Interrupt not requested

R (Note 1)

SIO5 receive interrupt request status bit

1: Interrupt requested

4–7

No function assigned. Fix to "0."

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

These registers indicate the transmit/receive interrupt requests from each SIO.

[Setting the interrupt request status bit]

This bit can only be set in hardware, and cannot be set in software.

[Clearing the interrupt request status bit]

This bit is cleared by writing "0" in software.

Note: • If the status bit is set in hardware at the same time it is cleared in software, the former has

priority and the status bit is set.

When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are

set to "0" and all other bits are set to "1." Those bits that have been set to "1" are unaffected by writing

in software and retain the value they had before the write.

12.2 Serial Interface Related Registers

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