32186 datasheet(562/1032 Pages) RENESAS

562 / 1032 page

SERIAL INTERFACE

12-14

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.2.2 SIO Transmit Control Registers

SIO0 Transmit Control Register (S0TCNT)

<Address: H'0080 0110>

SIO1 Transmit Control Register (S1TCNT)

<Address: H'0080 0120>

SIO2 Transmit Control Register (S2TCNT)

<Address: H'0080 0130>

SIO3 Transmit Control Register (S3TCNT)

<Address: H'0080 0140>

SIO4 Transmit Control Register (S4TCNT)

<Address: H'0080 0A10>

SIO5 Transmit Control Register (S5TCNT)

<Address: H'0080 0A20>

123456

TSTAT

TBE

TEN

CDIV

010

Bit Name

Function

0, 1

No function assigned. Fix to "0."

2, 3

CDIV

b2 b3 (Note 1)

BRG count source select bit

0: Select f(BCLK) or f(BCLK)/2

1: Select f(BCLK) or f(BCLK)/2 divided by 8

0: Select f(BCLK) or f(BCLK)/2 divided by 32

1: Select f(BCLK) or f(BCLK)/2 divided by 256

No function assigned. Fix to "0."

TSTAT

0: Transmission stopped and no data in transmit buffer register R

–

Transmit status bit

1: Transmitting now or data present in transmit buffer register

TBE

0: Data present in transmit buffer register

–

Transmit buffer empty bit

1: No data in transmit buffer register

TEN

0: Disable transmission

Transmit enable bit

1: Enable transmission

Note 1: The selection between f(BCLK) and f(BCLK)/2 is made with the SIOn Special Mode Register (SnSMOD).

(1) CDIV (BRG count source select) bits (Bits 2 and 3)

These bits select the count source for BRG (the Baud Rate Generator).

(2) TSTAT (Transmit Status) bit (Bit 5)

[Set condition]

This bit is set to "1" by a write to the transmit buffer register while transmission is enabled.

[Clear condition]

This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no

data exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit.

(3) TBE (Transmit Buffer Empty) bit (Bit 6)

[Set condition]

This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift

transmit enable bit to "0."

[Clear condition]

This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while

transmission is enabled (TEN = "1").

(4) TEN (Transmit Enable) bit (Bit 7)

Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0." If this bit is

cleared to "0" while transmitting data, the transmit operation stops.

12.2 Serial Interface Related Registers

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