32186 datasheet(563/1032 Pages) RENESAS

563 / 1032 page

SERIAL INTERFACE

12-15

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.2.3 SIO Transmit/Receive Mode Registers

SIO0 Transmit/Receive Mode Register (S0MOD)

<Address: H'0080 0111>

SIO1 Transmit/Receive Mode Register (S1MOD)

<Address: H'0080 0121>

SIO2 Transmit/Receive Mode Register (S2MOD)

<Address: H'0080 0131>

SIO3 Transmit/Receive Mode Register (S3MOD)

<Address: H'0080 0141>

SIO4 Transmit/Receive Mode Register (S4MOD)

<Address: H'0080 0A11>

SIO5 Transmit/Receive Mode Register (S5MOD)

<Address: H'0080 0A21>

123456

CKPOL

00000000

SEL3PNT

SELFST

SELCLK

CSIBL

Bit Name

Function

8–10

SMOD

b8 b9 b10

Serial interface mode select bit

0 : 7-bit UART

(Note 1)

1 : 8-bit UART

X : 9-bit UART

X : 8

−16-bit CSIO (Note 4)

CKS

0: Internal clock

Internal/external clock select bit

1: External clock

(Note 2)

STB

0: One stop bit

Stop bit length select bit, UART mode only

1: Two stop bits

(Note 3)

PSEL

0: Odd parity

Odd/even parity select bit, UART mode only

1: Even parity

(Note 3)

PEN

0: Disable parity

Parity enable bit, UART mode only

1: Enable parity

(Note 3)

SEN

0: Disable sleep function

Sleep select bit, UART mode only

1: Enable sleep function

(Note 3)

Note 1: For SIO2 and 3, bit 8 is fixed to "0" in hardware. This bit cannot be set to "1" in software (to select clock-synchronous serial

interface).

Note 2: Has no effect when UART mode selected.

Note 3: Bits 12–15 have no effect during clock-synchronous mode.

Note 4: The selection of CSIO bit length is made with the SIOn Special Mode Register (SnSMOD).

The SIO Transmit/Receive Mode Registers consist of bits to set the serial interface operation mode, data

format and the functions used during communication.

The SIO Transmit/Receive Mode Registers must always be set before the serial interface starts operating.

To change register settings after the serial interface starts sending or receiving data, first confirm that

transmit and receive operations have finished and then disable transmit/receive operations (by clearing

the SIO Transmit Control Register transmit enable bit and SIO Receive Control Register receive enable bit

to "0") before making changes.

(1) SMOD (Serial Interface Mode Select) bits (Bits 8–10)

These bits select the operation mode of serial interface.

(2) CKS (Internal/External Clock Select) bit (Bit 11)

This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is

selected, in which case the serial interface is clocked by the internal clock.

12.2 Serial Interface Related Registers

32186 Datasheet(PDF) 563 Page - Renesas Technology Corp

32186 Datasheet(HTML) 563 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL