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32186 Datasheet(PDF) 568 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 568 Page - Renesas Technology Corp |
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568 / 1032 page ![]() SERIAL INTERFACE 12 12-20 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 12.2.5 SIO Receive Buffer Registers SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144> SIO4 Receive Buffer Register (S4RXB) <Address: H'0080 0A14> SIO5 Receive Buffer Register (S5RXB) <Address: H'0080 0A24> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 RDATA ???????????????? <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 RDATA Received data is stored in these bits. R – Received data The SIO Receive Buffer Registers are used to store the received data. When the serial interface has finished receiving data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. These registers are a read-only register. Data must be LSB-aligned when latching a received data. According to the conditions of the serial interface mode select bit, the CSIO bit length select bit and the transfer order select bit, the data corresponding to the specified bit is received from the LSB or MSB side and an unused MSB side bit is set to “0.” When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial interface finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subsequent received data are not transferred to the Receive Buffer Register. To restart normal receive operation, clear the Receive Control Register REN (Receive Enable) bit to "0." Note: • For the 7-bit and 8-bit data formats, the register can be accessed bytewise. 12.2 Serial Interface Related Registers |
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