32186 datasheet(592/1032 Pages) RENESAS

592 / 1032 page

SERIAL INTERFACE

12-44

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.5 Notes on Using CSIO Mod

12.5 Notes on Using CSIO Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register

The SIO Transmit/Receive Mode Register, SIO Special Mode Register and SIOn Baud Rate Register and

the Transmit Control Register’s BRG count source select bit must always be set when the serial interface

is not operating. If a transmit or receive operation is in progress, wait until the transmit and receive opera-

tions are finished and then clear the transmit and receive enable bits before making changes.

• Settings of SIOn Baud Rate (SnBAUR)

Use caution when setting the SIOn Baud Rate (SnBAUR) so that the transfer rate does not exceed f(BCLK)/8.

• About successive transmission

To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer

• About reception

Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, trans-

mit operation must always be executed (by sending dummy data) even when the serial interface is

used for only receiving data. In this case, be aware that if the port function is set for the TXD pin (by

setting the operation mode register to "1"), dummy data may actually be output from the pin.

• About successive reception

To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer

• Transmission/reception using DMA

To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by

setting the DMA Mode Register) before serial communication starts.

• About reception finished bit

If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the

receive enable bit, and cannot be cleared by reading out the receive buffer register.

• About overrun error

If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO

Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer

subsequent received data is not stored in the receive buffer register (receive status bit = "1").

Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared

to "0." And this is the only way that the overrun error flag can be cleared.

• About DMA transfer request generation during SIO transmission

If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit

enable bit remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer

request is generated.

• About DMA transfer request generation during SIO reception

If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer

request is generated. Be aware, however, that if an overrun error occurred during reception, this DMA

transfer request is not generated.

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