32186 datasheet(844/1032 Pages) RENESAS

844 / 1032 page

WAIT CONTROLLER

18-2

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

18.1 Outline of Wait Controller

The Wait Controller controls the number of wait states inserted in bus cycles when accessing an external

extension area. The Wait Controller is outlined in the table below.

Table 18.1.1 Outline of the Wait Controller

Item

Description

Target space

Control is applied to the following address spaces depending on operation mode:

Single-chip mode:

No target space (Settings of the Wait Controller have no effect)

External extension mode: CS0 area (7 Mbytes), CS1 area (8 Mbytes),

CS2 area (8 Mbytes), CS3 area (8 Mbytes)

Processor mode:

CS0 area (8 Mbytes), CS1 area (8 Mbytes),

CS2 area (8 Mbytes), CS3 area (8 Mbytes)

Number of wait states

0–15 wait states set by software + any number of wait states set from the WAIT# pin

that can be inserted

During external extension and processor modes, four chip select signals (CS0# to CS3#) are output, each

corresponding to one of the four external extension areas referred to as CS0 through CS3.

18.1 Outline of Wait Controller

H'0000 0000

H'0010 0000

H'000F FFFF

H'0100 0000

H'007F FFFF

H'0200 0000

H'017F FFFF

H'0300 0000

H'027F FFFF

H'037F FFFF

H'0080 0000

H'00FF FFFF

H'0180 0000

H'01FF FFFF

H'0280 0000

H'02FF FFFF

H'03FF FFFF

H'0380 0000

Note 1. Non-CS0 area

Note: Ghost area should not be used intentionally during programing.

Internal ROM

area (Note 1)

CS0 area

(7MB)

CS1 area

(8MB)

CS2 area

(8MB)

CS3 area

(8MB)

CS0 area

(8MB)

CS1 area

(8MB)

CS2 area

(8MB)

CS3 area

(8MB)

Non-CS0 area

(Internal ROM access area)

Ghost area

(8MB)

Ghost area

(8MB)

Ghost area

(8MB)

Ghost area

(8MB)

Ghost area

(8MB)

Ghost area

(8MB)

Figure 18.1.1 CS0–CS3 Area Address Map

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