32186 datasheet(847/1032 Pages) RENESAS

847 / 1032 page

WAIT CONTROLLER

18-5

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

18.2 Wait Controller Related Registers

The operation is not guaranteed if the settings listed in the Table 18.2.1 are selected.

Table 18.2.1 List of Prohibited Settings

CLKOSEL

WAIT

CWAIT

SWAIT

RECOV

IDLE

0000

–

0000

–

0000

–

0000

–

0001

–

0000

–

0001

–

0001

–

Note: • " – " = Don't Care

If a read cycle is followed immediately by a write cycle, one idle cycle is inserted unless RECOV bit = 1 and

IDLE bit = 0. Table 18.2.2 shows the relationship between RECOV bit and IDLE bit settings and the num-

ber of idle cycles inserted after the bus cycle.

Table 18.2.2 RECOV Bit and IDLE Bit Settings and the Number of Idle Cycles Inserted after Bus Cycle

RECOV

IDLE

Read (Followed by Write)

Read (Followed by Read)

Write

(Note 1)

Note 1: The number of cycles inserted when instruction fetch access occurs back-to-back, or operand access is performed

successively by a word (32-bit) access. In other cases (if operand access is performed successively, instruction fetch

access is followed by operand access or operand access is followed by instruction fetch access), a 1-cycle idle cycle

is inserted.

Note: • Under each of the above conditions, no recovery cycle is inserted when RECOV bit = 0, and one recovery cycle is

inserted when RECOV bit = 1.

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