32186 datasheet(896/1032 Pages) RENESAS

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JTAG

21-2

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

21.1 Outline of JTAG

The M32R/ECU contains a JTAG (Joint Test Action Group) interface compliant with IEEE Standard Test

Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used

as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG

test access ports, see IEEE Std. 1149.1a-1993 documentation.

Note: • The JTAG interface in the M32R/ECU is used to connect a JTAG emulator during debugging as

well. In this chapter, the JTAG interface is explained assuming its use as an input/output path

for boundary-scan test.

Functions of the JTAG interface-related pins mounted on the M32R/ECU are shown below.

Table 21.1.1 JTAG Pin Functions

Type

Pin Name Signal Name

I/O

Function

TAP

JTCK

Test clock

Input

Clock input to the test circuit.

(Note 1) JTDI

Test data Input

Input

Synchronous serial data input pin used to supply the test instruction

code and test data.

This input is sampled on the rising edge of JTCK.

JTDO

Test data Output Output

Synchronous serial data output pin used to output the test instruction

code and test data. This signal changes state on the falling edge of JTCK,

and is output in only the Shift-IR or Shift-DR state. Otherwise, it goes to a

high-impedance state.

JTMS

Test mode select Input

Test mode select input to control the test circuit’s state transition. This input is

sampled on the rising edge of JTCK.

JTRST

Test reset

Input

Active "L" test reset input to initialize the test circuit asynchronously. To

ensure that the test circuit is reset without fail, JTMS input signal must be

held "H" while this signal changes state from "L" to "H."

Note 1: TAP stands for Test Access Port (JTAG interface specified in IEEE 1149.1).

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